Parallel Prefix Algorithms on the Multicomputer

A family of computation-efficient parallel prefix algorithms for message-passing multicomputers are presented. The family generalizes a previous algorithm that uses only half-duplex communications, and thus can improve the running time. Several properties of the family are derived, including the number of computation steps, the number of communication steps, and the condition for effective use of the family. The family can adopt collective communication operations to reduce the communication time, and thus becomes a second family of algorithms. These algorithms provide the flexibility of choosing either less computation time or less communication time, depending on the characteristics of the target machine, to achieve the minimal running time. Key-Words: Computation-efficient, Cost optimality, Half-duplex, Message-passing multicomputers, Parallel algorithms, Prefix computation